1. Field of the Invention:
This invention relates to semiconductor memory systems and particularly to information sense amplifiers for differentially sensing information signals provided by stored charge memory cells.
2. The Prior Art:
The single FET/capacitor storage cell, see U.S. Pat. No. 3,387,286, "Field Effect Transistor Memory," R. H. Dennard, assigned to the assignee of the instant invention, is attractive for semiconductor memories because of its small area and relatively simple structural requirements. However, one of the major design difficulties in implementing such memory systems lies in the difficulty in detecting information signals. Because of the severe attenuation of the stored signal during a read operation, when the stored charge is redistributed between the cell storage capacitance and the comparatively large bit/sense line capacitance, difficult design barriers are faced in order to improve the density of the storage circuits in order to reduce production costs. As a result, unless very sensitive sense amplifiers are used, storage capacitances must be large, thus increasing the cell area. An alternative solution is to limit the number of bits per bit/sense line and/or sense amplifier. This not only requires more sense amplifiers but makes the topological design of a high density memory chip rather difficult. One design approach previously utilized to improve the ratio of storage capacitance to bit line capacitance has been the use of a split memory array in which a centrally located differential sense amplifier including a cross-coupled regenerative FET latch circuit. Although different specific circuit designs have been previously proposed for such amplifiers, they may be generally divided into two types, both of which may be embodied in static or dynamic logic configurations. In the first type, the memory bit lines are initially precharged to a relatively high potential. A charged or uncharged memory capacitor is coupled to one bit line and a reference potential, provided by a dummy storage cell, is coupled to the other bit line creating a differential input signal. The cross-coupled regenerative latch is then energized such that a race discharge condition is initiated. The cross-coupled FET having its gate connected to the bit line with the higher potential will become conductive as its source is pulled down and will discharge the lower potential bit line. The bit line with the higher potential will maintain its original potential. An example of this type of sense amplifier is described in U.S. Pat. No. 3,678,473, entitled, "Read-Write Circuit for Capacitive Memory Arrays," to S. E. Wahlstrom. The second type of sense amplifier initially precharges the bit lines to ground potential and after introducing a differential signal, by coupling a storage capacitor to one of the bit lines, activates the sense amplifier by charging the bit lines up until one of the cross-coupled FET's reaches a threshold potential in which case the sense amplifier latch is then set. An example, of this type is described in U.S. Pat. No. 3,838,404, entitled "Random Access Memory System and Cell," to R. H. Heeren. A variant of the second type, in which the bit lines are partially charged to an intermediate voltage in order to reduce the time necessary to reach a threshold voltage is also described in the last referred to patent. Although such sense amplifiers are widely utilized in industry they are still subject to the limitation provided by the ratio of storage capacitance to bit line capacitance. In addition, any device imbalances, such as differences in threshold voltage, will cause further insensitivity of the sense amplifier.
Additional improvements in FET sense amplifier design are taught in U.S. Pat. No. 3,764,906, entitled "Stored Charge Detection by Charge Transfer," issued Oct. 9, 1973, to L. G. Heller and assigned to the instant assignee, which teaches a charge transfer, or bucket brigade, sensing technique which is independent of device parameters and can effectively transfer potentials on the storage capacitor directly to the sense node, irrespective of the bit line capacitance. This technique although more sensitive to input voltages, is slower than the dynamic latch due to the time required to fully charge the large bit/sense line capacitance through an FET approaching cut off while operating in its saturation region. Improvements in charge transfer sense amplifiers are found in U.S. Pat. No. 3,760,381, entitled "Stored Charge Memory Detection Circuit," issued Sept. 18, 1973, to Y. L . Yao, and assigned to the instant assignee, and in the article, "Differential Sense Amplifier," by D. P. Spampinato, IBM Technical Disclosure Bulletin, November 1974, pages 1797-8. These last two references utilize the charge transfer circuit as a preamplifier for a differential sense latch.,
Another problem confronted by circuit designer of single FET/capacitor memory arrays is that of providing necessary support circuitry on the semiconductor chip for writing information into the memory array as well as sensing data stored in the array. When using the sense amplifiers described above, in which the bit lines are initially precharged to a high potential, and in the case of charge transfer sense amplifiers, a particular support circuitry design problem becomes apparent. In order to achieve optimum performance in the memory, design criteria dictates that the precharge potential as well as the stored data charge potential be as close as possible to the maximum available supply potential provided to the semiconductor chip. When such a criteria is dictated by other considerations, it then becomes necessary to directly drive both bit lines coupled to the sense amplifier in order to properly write data into both halves of the memory array. This problem has been solved in the past by designing memory arrays in which the bit line decoders and the sense amplifiers are both placed in the central portion of the memory array. Unfortunately, this approach makes it difficult to provide paths for data between the bit decoders and the data input/output pads, normally located at the edge of the semiconductor chip. Another approach is to provide two sets of bit decoders, one for each bit line, at the expense of silicon area. Both solutions are hardly efficient when the overall objective is to obtain maximum memory array density on the chip. Although it is possible to write data by driving only a single bit line when using a sense amplifier which utilizes bit line precharging potentials which are lower than the highest available supply potential, such a result is achieved only through a loss of performance and increases in the complexity of timing signals required to operate the memory.